System architecture for Intel x86 based personal computer is divided in two subsystems known as North block and South Block as shown above . North block contains CPU cores along with DRAM controller , Graphics Subsystems and other PCI express controllers hence known as CPU subsystem while South block contains most of other peripherals like Wireless Connectivity , USB , LAN etc. and known as Platform controller hub (PCH). Both North block and South block are connected via DMI (Direct Media Interface) interface. Red arrows show different path of communication from CPU to peripherals as addressed via their mapped memory address.

Operating Mode of x86 Processor

x86 based processor operates in below three modes as shown in above diagram:-

• Real Mode – Once System start, its starts in real Mode.
• Protected Mode – Native Mode of Processor execution
• System Management Mode (SMM) – For Hardware Security etc., operating system would provide access to this via SMI ( System Management Interrupt).

System Memory Address Range

Above is an pictorial view of how system memory gets mapped for each peripheral and what ranges are available to Operating system to operate. Here some memory areas are reserved by BIOS for system related functionality like Flash Image , APIC ,PCI Config Space and Integrated Graphics etc. Any memory address falling in PCI Config range is actually a memory mapped read/write for configured peripherals in that PCI address range.

Memory Management

Two ways , x86 based system performs memory management.

• Segmentation
• Paging

Segmentation

As segmentation and Paging seems to perform the same functionality like providing memory isolation for all programs/processes, Segmentation is used in very limited way in Linux . Moreover x86-64 architecture does not use segmentation in long mode (64-bit mode).Four of the segment registers: CS, SS, DS, and ES are forced to 0, with the limit to 2^64 .

Paging

Paging is the process of translating Virtual Memory Address ( also called linear address) so that they can be used to access physical memory or I/O Devices (through memory mapped addresses). As it can be seen that for translating virtual memory address to physical address, page tables are maintained .

CPU Cache Memory

CPU cores configure internal RAM as multilevel cache (L1/L2/L3) .These RAMs are static RAMs which are faster than DRAMs which are used as main memory chip or RAM for x86 system. L1 caches are per Core while L2 caches are across cores and L3 cache is across sockets containing multiple cores. Separate L1 caches are maintained for instruction and data. MTRR ( Memory type range registers) are used to configure memory ranges for each of these caches. These caches configuration might vary based on different processors sets.

TLBs ( Translation lookaside buffers) are maintained to cache page tables. Separate TLBs are maintained for instruction and data. Default cache line size is 64 byte on x86-64 based system.

CPU Registers

Basic Execution environment on x86-64 consists of 16 General purpose registers with each register having a 64-bit width. Beside this , it has Instruction pointer register known as RIP and System Flag register known as RFLAGS which are also 64-bit in width.

Interrupt Controller

APICs are advanced programmable interrupt controller which receive inputs from different peripheral as interrupt and sends these signals to processor core . I/O APIC is part of Intel’s system chipset ( i.e. PCH) which actually does the job of routing interrupts from different peripherals to CPU’s local APIC. Beside this , in multi processor system, IPIs ( Inter processor interrupt) are sent among each logical processor or core. The purpose of IPI messages are to distribute interrupts among the processors in the system or to execute system wide functions (such as, booting up processors or distributing work among a group of processors).

PCI Bus topology and PCI Config Space

x86 based CPU’s North and South Blocks are structured in form of PCI BUS topology. Each Peripheral is enumerated by BIOS as a PCI device and will be located at a specific Bus, Device and Function ID . Each PCI device would have PCI config space allocated as shown below where specific details about that device like device ID, vendor ID, physical memory mapped address, interrupt support etc. would be stored in memory.